1. Field of the Invention The present invention relates to a drive circuit for driving a power semiconductor element and, more particularly to a drive circuit capable of avoiding a malfunction by removing asynchronous error signals as well as synchronous error signals.
2. Background Art
In ordinary cases of driving a half-bridge-connected power semiconductor element (MOSFET, IGBT or the like) with a high-withstand-voltage integrated circuit (HVIC), the load on the power semiconductor element is an inductive load (L) such as a motor or a fluorescent lamp. A transient change in high-side reference voltage (VS) on the HVIC to the negative side with respect to ground (GND) occurs at the time of switching under the influence of this inductive load and a parasitic L component or the like due to wiring on a printed circuit board or the like. At the time of return from the change to the negative (voltage) side, a recovery current flows from the high-side power supply (VB) through a level shift resistor as a drain current in the level-shifting high-withstand-voltage MOSFET. There is a possibility of this current being erroneously recognized as a high-side input signal to cause a malfunction of the high-side circuit and an abnormal signal output in the output (upper arm control signal) from the high-side circuit. A fault such as an arm short circuit may result in such a case. In some case, such a malfunction occurs due to dv/dt applied to Vs (see, for example, Japanese Patent Laid-Open No. 2003-133927).
To avoid this fault, a system in which a level shift signal is selected by means of a CR filter and a logic filtering system in which simultaneous input of error signals to an “RS flip flop” incorporated in the high-side circuit is excluded by a logic circuit (see for example, Japanese Patent Laid-Open No. 2001-145370).
A difference in malfunctioning signal margin exists between an element constituting the level shift circuit on the on-signal side and an element constituting the level shift circuit on the off-signal side due to manufacturing variation. Also, if the time period during which a recovery current due to negative noise in VS flows and the time period during which the off signal is generated overlap each other, the duration of the recovery current flowing through the level-shifting high-withstand-voltage MOSFET on the on side is longer than that of the recovery current flowing on the off side. In such a case, error signals not synchronous with each other (hereinafter referred to as asynchronous error signals) are generated in which the rise or fall times at which the on and off signals rise (from “L” to “H”) or fall (from “H” to “L”) do not coincide with each other or noncoincidence occurs both between the rise times and between the fall times. The conventional circuit, however, is capable of removing error signals generated on the on-signal side and the off-signal side simultaneously with each other and coinciding with each other in rise and fall times (hereinafter referred as synchronous error signals) but incapable of removing asynchronous error signals.